The escalating requirements for high density and performance associated with ultra large scale integration semiconductor wiring require responsive changes in interconnection technology. Such escalating requirements have been found difficult to satisfy in terms of providing a low RC (resistance capacitance) interconnection pattern, particularly wherein submicron vias, contacts and trenches have high aspect ratios due to miniaturization.
Conventional semiconductor devices typically comprise a semiconductor substrate, normally of doped monocrystalline silicon, and a plurality of sequentially formed interdielectric layers and conductive patterns. An integrated circuit is formed containing a plurality of conductive patterns comprising conductive lines separated by interwiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines and logic interconnect lines. Typically, the conductive patterns on different layers, i.e., upper and lower layers, are electrically connected by a conductive plug filling a via opening, while a conductive plug filling a contact opening establishes electrical contact with an active region on a semiconductor substrate, such as a source/drain region. Conductive lines formed in trenches typically extend substantially horizontal with respect to the semiconductor substrate. Semiconductor "chips" comprising five or more levels of metallization are becoming more prevalent as device geometries shrink to submicron levels.
A conductive plug filling a via opening is typically formed by depositing an interdielectric layer on a conductive layer comprising at least one conductive pattern, forming an opening in the interdielectric layer by conventional photolithographic and etching techniques, and filling the opening with a conductive material, such as tungsten (W). Excess conductive material on the surface of the interdielectric layer can be removed by chemical-mechanical polishing (CMP). One such method is known as damascene and basically involves forming an opening and filling the opening with a metal. Dual damascene techniques involve forming an opening comprising a lower contact or via opening section in communication with an upper trench section, and filling the opening with a conductive material, typically a metal, to simultaneously form a conductive plug in electrical contact with a conductive line.
High performance microprocessor applications require rapid speed of semiconductor circuitry. The control speed of semiconductor circuitry varies inversely with the resistance and capacitance of the interconnection pattern. As integrated circuits become more complex and feature sizes and spacings become smaller, the integrated circuit speed becomes less dependent upon the transistor itself and more dependent upon the interconnection pattern. Miniaturization demands long interconnects having small contacts and small cross-sections. As the length of metal interconnects increases, and cross-sectional areas and distances between interconnects decrease, the RC delay caused by the interconnect increases. If the interconnection node is routed over a considerable distance. e.g., hundreds of microns or more, as in submicron technologies, the interconnection capacitance limits the circuit node capacitance loading and, hence, the circuit speed. As design rules are reduced to about 0.18 micron and below, the rejection rate due to integrated circuit speed delays severely limits production throughput and significantly increases manufacturing costs. Moreover, as line widths decrease, electrical conductivity and electromigration resistance become increasingly important.
Cu and Cu alloys have received considerable attention as a replacement material for Al in VLSI interconnection metallizations. Cu is relatively inexpensive, easy to process, has a lower resistivity than Al, and has improved electrical properties vis-a-vis W, making Cu a desirable metal for use as a conductive plug as well as conductive wiring. An approach to forming Cu plugs and wiring comprises the use of damascene structures employing CMP, as in Teong, U.S. Pat. No. 5,693,563. However, due to Cu diffusion through the interdielectric layer, Cu interconnect structures must be encapsulated by a diffusion barrier layer. Typical diffusion barrier metals include tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium tungsten (TiW), tungsten nitride (WN) and silicon nitride (Si.sub.3 N.sub.4) for encapsulating Cu. The use of such barrier materials to encapsulate Cu is not limited to the interface between Cu and the interdielectric layer, but includes interfaces with other metals as well.
There are additional problems attendant upon conventional Cu interconnect methodology. For example, conventional practices comprise forming a damascene opening in an interdielectric layer and depositing a barrier layer, such as Ta or TaN, lining the opening and on the interdielectric layer. Cu or a Cu alloy is then deposited on the barrier layer filling the opening. CMP is then conducted employing an abrasive slurry. Conventional CMP slurries are typically aqueous suspensions comprising a particulate abrasive, such as alumina, an organic dispersant, and a suitable oxidizing agent. Other adjuvants can be employed to improve dispersibility or enhance performance. In CMP Cu and Cu alloy metallization, the CMP slurry typically contains a relatively large amount of a relatively hard abrasive particulate material, such as alumina, e.g. about 2 to about 3 wt. % of alumina. However, it was found that during conventional CMP, the planarized Cu or Cu alloy surface undergoes abrasion, i.e., scratching. In addition, conventional practices typically comprises mechanically removing remaining or residual slurry particles after CMP, as by buffing with water on a secondary platen buff pad, or by scrubbing with a polyvinyl acetate (PVA) foam brush material on a wafer scrubbing tool. Such mechanical removal of slurry particles is not particularly effective and may cause further scratching of the Cu surface.
Accordingly, there exists a need for CMP Cu methodology which enables a high degree of planarization without surface abrasion and which facilitates removal of residual abrasive slurry particles subsequent to CMP with a high degree of efficiency.